A conventional MOS transistor may include a gate pattern formed on a semiconductor substrate, a channel region defined below the gate pattern, and source/drain regions formed in the semiconductor substrate on both sides of the channel region. Generally, the source/drain regions may include a lightly doped drain (LDD) structure for example, to reduce and/or suppress hot carrier effects. More specifically, by lowering the impurity concentration of the source/drain regions adjacent to a channel region, the electric field concentration may be reduced, which may suppress hot carrier effects.
A method for forming a conventional MOS transistor will now be described with reference to FIG. 1. As illustrated in FIG. 1, a gate pattern 5 is formed on a semiconductor substrate 1. The gate pattern 5 includes a gate oxide layer 2, a gate electrode 3, and a capping pattern 4, which may be sequentially stacked. The substrate 1 below the gate pattern 5 is defined as a channel region. Using the gate pattern 5 as a mask, impurities may be implanted at a relatively low dose to form a lightly doped layer 6.
A gate spacer 7 may be formed on opposing sidewalls of the gate pattern 5. Using the gate pattern 5 and the gate spacer 7 as a mask, impurities may be implanted at a relatively high dose to form a heavily doped layer 8. Since the lightly doped layer 6 may have a shallower junction than the heavily doped doping layer 8, the source/drain region 9 formed at both sides of the channel region may have a lightly-doped drain (LDD) structure, including the lightly and heavily doped layers 6 and 8.
In recent years, there has been demand for semiconductor devices with increasingly high operating speeds. As such, MOS transistors with increased on-current have been provided. However, MOS transistors including the above LDD structure may suffer from decreased on-current, due to the relatively high resistance of the lightly doped layer 6.
Many efforts have been made to increase on-current in MOS transistors. For example, the lightly doped layer 6 may be doped to have an impurity concentration similar to that of the heavily doped layer 8. However, as the impurity concentration of the lightly doped layer 6 increases, the junction depth of the lightly doped layer 6 may increase, due to diffusion of the impurities. Thus, short channel effects may become severe enough to degrade characteristics of the MOS transistor.